Filling cavities in an integrated circuit and resulting devices

ABSTRACT

A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. application Ser. No.14/711,380, filed May 13, 2015, the content of which is incorporatedherein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to designing and fabricatingintegrated circuit (IC) devices. The present disclosure is applicable tofilling cavities in an IC device without having voids or gaps in 22nanometer technology nodes and beyond.

BACKGROUND

Generally, in the fabrication of an IC device, photolithographicprocesses may be utilized to print/pattern cavities, trenches, and/orrecessed-areas for creating various devices, elements, and circuits.Different types of cavities may be formed at different stages of thefabrication process. For instance, the cavities may have differentshapes, depths and/or sizes and may be created in different regions of asubstrate. For example, a cavity intended to form a contact may have onesize and aspect ratio (e.g., depth to width ratio), may be at a certainlocation in the substrate, and may be filled with a particular materialsuch as tungsten (W), whereas trenches for metal lines may have adifferent size and aspect ratio and may be filled with a differentmaterial such as copper (Cu). The metal line trenches or channels in ametal layer may be filled with Cu for interconnecting different devicesin the IC whereas a shallow trench isolation (STI) region may be filledwith an oxide for electrically isolating various devices from eachother. In the semiconductor industry, advanced technologies are used todesign and manufacture smaller IC devices that may include circuitelements (e.g., transistor, interconnecting wires, vias, etc.) withsmaller geometries. However, in smaller IC devices, the cavities thatare to be filled with different materials may also shrink, which maypresent various challenges. For example, a trench filled with a material(e.g., Cu) may be filled such that void spots/areas may develop, whichmay be due insufficient/irregular filling of the material. The voids maydegrade interconnectivities between various layers or elements in the ICdevice and cause performance or reliability issues. The voids may, forinstance, be due to a high aspect ratio of a trench (e.g., too deep)where the filling material may not fully fill the trench.

FIG. 1A is a cross sectional diagram of various layers in an example ICdevice. FIG. 1A illustrates stack 100 including an interlayer dielectric(ILD) 101 over a silicon (Si) substrate (not shown for illustrativeconvenience), active area and gate contacts (e.g., W) 103 a through 103d, an etch stop layer 105, another ILD 107, a dielectric hard-mask (DHM)layer 109 (such as silicon oxynitride (SiON)), a metal hard-mask (MHM)layer 111 (e.g., titanium nitride (TiN)), and a metal (e.g., Cu) layer113 formed on upper surface of the MHM layer 111. Additionally, themetal layer may fill cavities/trenches 115 and 117 (e.g., via or metalline trenches) that may have been formed by various IC manufacturing(e.g., litho-etch) processes. A thin barrier/seed layer 119 may beformed in the cavities, prior to filling with metal.

FIGS. 1B and 1C illustrate cross-sectional views of structures in anexample IC device. In FIG. 1B, image 121 includes a trench 115, which isfilled with a material (e.g., Cu); however, there is a void 123 that maybe due to insufficient filling material. Also, FIG. 1C depicts image 125that illustrates a different view of the void 123.

As illustrated, different cavities/trenches (e.g., 115 or 117) may be atdifferent depths yielding different aspect ratios. In instances of adeep trench (e.g., high aspect ratio), it is possible that the trenchmay not be completely filled with an intended material, wherein voids orgaps may exist. As noted, such voids or gaps may contribute toperformance or reliability issues in an IC device.

A need therefore exists for a methodology enabling filling of highaspect ratio cavities, with no voids or gaps, in an IC device and theresulting device.

SUMMARY

An aspect of the present disclosure is an IC device that includes adecreased aspect ratio of cavities in a substrate, wherein the cavitiesmay be filled with respective materials and without voids or gaps in thefilling materials.

Another aspect of the present disclosure is a method for decreasingaspect ratio of cavities in a substrate, wherein the cavities may befilled with respective materials and without voids or gaps in thefilling materials.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure some technical effects may beachieved in part by a method including providing active area and/or gatecontacts in a first ILD; forming selective protective caps on uppersurfaces of the contacts; forming a second ILD on upper surfaces of theprotective caps and on an upper surface of the first ILD; forming ahard-mask stack on the second ILD; forming, in the second ILD andhard-mask stack, cavities exposing one or more protective caps; removingselective layers in the stack to decrease depths of the cavities; andfilling the cavities with a metal layer, wherein the metal layer in oneor more cavities connects to an upper surface of the one or more exposedprotective caps.

One aspect includes performing chemical mechanical polishing (CMP) priorto forming the selective protective caps. Another aspect includesforming an etch stop layer prior to forming the second ILD.

In one aspect, the forming of the hard-mask stack includes forming afirst dielectric hard-mask (DHM1) layer, a metal hard-mask (MHM) layer,a second dielectric hard-mask (DHM2) layer, a spin-on hard-mask (SOH)layer, and an antireflective coating (ARC) hard-mask layer.

In some aspects, the selective layers include the MHM layer, the DHM2layer, the SOH layer, and the ARC layer.

In another aspect, the method includes conformally forming, prior toforming the metal layer, a barrier metal/seed layer on exposed surfacesof the DHM1 and ILD layers. In one aspect, the method includes removingan upper portion of the one or more exposed protective caps.

In some aspects, the MHM layer is removed at a faster rate than theupper portion of the one or more exposed protective caps. In anotheraspect, the method includes performing CMP down to an upper surface ofthe second ILD subsequent to filling with the metal layer. In oneaspect, the protective caps comprise ruthenium caps. In another aspect,the contacts are cavities filled with tungsten.

In another aspect, the cavities include interconnecting vias andtrenches.

In one aspect, the metal includes copper, and the method furtherincludes filling the cavities with the copper by electrochemical plating(ECP).

According to the present disclosure, some technical effects may beachieved in part by a device including active area and/or gate contactsin a first ILD; selective protective caps on upper surfaces of thecontacts; a second ILD on upper surfaces of the protective caps and onan upper surface of the first ILD; and vias through the second ILD downto the protective caps.

In one aspect, the device includes metal line trenches in the secondILD.

In another aspect, the device includes an etch stop layer under thesecond ILD. In one aspect, the protective caps include ruthenium.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIG. 1A is a cross-sectional diagram of various layers in an example ICdevice;

FIGS. 1B and 1C illustrate cross-sectional views of structures withvoids in an example IC device; and

FIGS. 2A through 2I schematically illustrate a process flow for reducingaspect ratios of cavities in an IC device and enabling defect-freefilling of the cavities, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments. Inaddition, unless otherwise indicated, all numbers expressing quantities,ratios, and numerical properties of ingredients, reaction conditions,and so forth used in the specification and claims are to be understoodas being modified in all instances by the term “about.”

The present disclosure addresses and solves the problem of voids andirregular gaps in cavities in an IC device attendant upon filling thecavities with respective materials. The present disclosure addresses andsolves such problems, for instance, by, inter alia, removing one or morelayers of materials in the IC device to reduce the aspect ratio (e.g.,depth) of cavities in a substrate so that the cavities may be filledwith respective materials and without voids or gaps in the filling.

FIGS. 2A through 2I schematically illustrate a process flow for reducingaspect ratios of cavities in an IC device and enabling defect-freefilling of the cavities, in accordance with an exemplary embodiment.

FIG. 2A illustrates the ILD 101 including the active area and gatecontacts 103 a through 103 d that may be formed of a material such as W.After planarizing (e.g., by a CMP process) the contacts down to theupper surface of the ILD 101, as illustrated in FIG. 2B, ruthenium (Ru)protective caps 201 a through 201 d may be selectively deposited on theupper surfaces of the W contacts 103 a through 103 d. The deposition ofthe Ru caps 201 a through 201 d may be by use of a thermal chemicalvapor deposition process. In FIG. 2C, an etch stop layer 105 is formedon the upper surface of the ILD 101 and upper surfaces of the Ru caps201 a through 201 d. An ILD layer 107 (e.g., a low-k dielectric materialsuch as silicon oxycarbonitride) is then formed. Metal line trenches andvias will be formed in and through the ILD layer 107. A DHM1 layer 109,a MHM layer 111, a second DHM (DHM2) layer 203, a SOH layer 205, and anARC layer (e.g., SiON) 207 for etch transfer and reflection control arethen formed consecutively over the ILD layer 107.

In FIG. 2D, various available IC fabrication processes (e.g., litho-etchdouble patterning) may be utilized to create cavities 209 for metal linetrench patterning. Then the SOH layer 205 and ARC hard-mask layer 207may be removed. In FIG. 2E, another SOH layer 205 may be deposited inthe cavities 209 and on the upper surfaces of the remaining sections ofthe DHM2 layer 203. Additional layers, e.g., a SiON layer 211; abottom-antireflective-coating (BARC) layer 213, and a photoresist layer215, are, respectively, formed on the upper surface of the SOH layer 205for via patterning.

In FIG. 2F, various IC fabrication processes may be utilized to createcavities 217 and 219, wherein the cavities 217 (e.g., metal linetrenches) may extend into the ILD layer 107. The cavities 219 (e.g.,vias) may extend deeper, through the ILD layer 107, down to and exposingupper surfaces of the Ru caps 201 c and 201 d. During the full etch ofmetal line trenches 217 and vias 219, the remaining sections of the DMH2layer 203, SOH layer 205, SiON layer 211, BARC layer 213, andphotoresist 215 are removed leaving sections of the MHM layer 111 on topof the stack. As illustrated, a cavity 217 may be at a depth of 221 aand at a width of 223. Similarly, a cavity 219 may be associated with adepth of 221 b and a width similar to width 223.

In FIG. 2G, various IC fabrication processes (e.g., wet clean) may beutilized to etch and remove remaining sections of the MHM layer 111 andan upper portion of each of the Ru caps 201 c and 201 d leaving partialRu caps 225 and 227. It is noted that chemicals used in the etchingprocess may etch the MHM/TiN layer 111 at a faster rate (e.g., 320nanometer/minute) than the Ru caps 201 c and 201 d (e.g., less than onenanometer/minute); therefore, even after etching away the TiN layer 111,the partial Ru caps 225 and 227 still remain to protect the W contacts103 c and 103 d. As illustrated, removal of the TiN layer 111 of FIG. 2Fmay decrease the depth of a cavity 217 from 221 a to 221 c, which maydecrease the aspect ratio for that cavity by a percentage (e.g., 17%).Similarly, the depth of a cavity 219 may decrease from the depth of 221b to 221 d, which may decrease the aspect ratio for that cavity by anassociated percentage (e.g., 11%). In FIG. 2H, a thin barrier metal/seedlayer 119 is formed on the upper surface of the remaining sections ofthe DHM1 layer 109 as well as in the cavities 217 and 219 includingsidewalls therein; however, the upper surfaces of the partial Ru caps225 and 227 remain exposed and without barrier metal/seed layer 119 ontheir upper surfaces. Next, a metal layer 113 is formed in thecavities/trenches 217 and 219 on the upper surface of the barriermetal/seed layer 119 by electrochemical plating (ECP). The metal layer113 may form a direct contact with the partial Ru caps 225 and 227. InFIG. 2I, an upper portion of the metal layer 113 and remaining sectionsof the DHM1 layer 109 are removed by planarization (e.g., CMP) down toan upper surface of the ILD layer 107 leaving the cavities 217 and 219filled with remaining portions of the metal layer 113.

It is noted that other typical materials and IC fabrication processesmay be utilized. The process may be used for all metal layers andcontact layers, where the via bottom may be W or Cu.

The embodiments of the present disclosure can achieve several technicaleffects, including reduced aspect ratio of cavities in a substrate forenabling defect-free filling of the cavities with respective materialsas well as protection of the via bottoms from wet TiN removal. Further,the embodiments enjoy utility in various industrial applications as, forexample, microprocessors, smart phones, mobile phones, cellularhandsets, set-top boxes, DVD recorders and players, automotivenavigation, printers and peripherals, networking and telecom equipment,gaming systems, digital cameras, or other devices utilizing logic orhigh-voltage technology nodes. The present disclosure therefore enjoysindustrial applicability in any of various types of highly integratedsemiconductor devices, including devices that use SRAM memory cells(e.g., liquid crystal display (LCD) drivers, synchronous random accessmemories (SRAM), digital processors, etc.), particularly for 22 nmtechnology node devices and beyond.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A device comprising: active area and/or gatecontacts in a first interlayer dielectric (ILD); selective protectivecaps on upper surfaces of the contacts; a second ILD on upper surfacesof the protective caps and on an upper surface of the first ILD; andvias through the second ILD down to the protective caps.
 2. The deviceaccording to claim 1, further comprising metal line trenches in thesecond ILD.
 3. The device according to claim 1, further comprising anetch stop layer under the second ILD.
 4. The device according to claim1, wherein the protective caps comprise ruthenium.
 5. A devicecomprising: active area and/or gate contacts in a first interlayerdielectric (ILD); selective protective caps on upper surfaces of thecontacts; a second ILD on upper surfaces of the protective caps and onan upper surface of the first ILD; a hard-mask stack on the second ILD;cavities, in the second ILD and hard-mask stack, exposing one or moreprotective caps; and a metal layer filling the cavities, wherein themetal layer in one or more cavities connects to an upper surface of theone or more exposed protective caps, wherein the hard-mask stackcomprises: a first dielectric hard-mask (DHM1) layer, a metal hard-mask(MHM) layer, a second dielectric hard-mask (DHM2) layer, a spin-onhard-mask (SOH) layer, and an antireflective coating (ARC) hard-masklayer; and wherein the protective caps comprise ruthenium caps and thecontacts are cavities filled with tungsten.
 6. The device according toclaim 1, further comprising: a barrier metal/seed layer on exposedsurfaces of the DHM1 and ILD layers.
 7. The device according to claim 5,wherein the cavities include interconnecting vias and trenches.
 8. Thedevice according to claim 5, wherein the metal comprises copper.
 9. Adevice comprising: active area and/or gate contacts in a firstinterlayer dielectric (ILD); selective protective caps on upper surfacesof the contacts; a second ILD on upper surfaces of the protective capsand on an upper surface of the first ILD; a hard-mask stack on thesecond ILD, wherein the hard-mask includes a first dielectric hard-mask(DHM1) layer, a metal hard-mask (MHM) layer, a second DHM dielectrichard-mask (DHM2) layer, a spin-on hard-mask (SOH) layer, and anantireflective coating (ARC) hard-mask layer; cavities, in the secondILD and hard-mask stack, exposing one or more protective caps; a metallayer in the cavities, wherein the metal layer in one or more cavitiesconnects to an upper surface of the one or more exposed protective caps;and a barrier metal/seed layer on exposed surfaces of the DHM1 and ILDlayers, wherein the protective caps comprise ruthenium caps, thecontacts are cavities filled with tungsten.
 10. The device according toclaim 9, further comprising metal line trenches in the second ILD. 11.The device according to claim 9, further comprising an etch stop layerunder the second ILD.
 12. The device according to claim 9, wherein theprotective caps comprise ruthenium.
 13. The device according to claim 9,wherein the cavities include interconnecting vias and trenches.
 14. Thedevice according to claim 9, wherein the metal comprises copper.